1. Field of the Invention
The present invention relates to a semiconductor memory apparatus, and in particular to a sense amplifier for a dynamic random access (DRAM) semiconductor memory apparatus which is formed of both p-channel and n-channel metal-oxide-silicon (MOS) transistors.
2. Description of the Related Art
In a DRAM semiconductor memory apparatus, sense amplifiers (which serve to detect and amplify small voltages that are produced on bit lines as a result of read-out of data from memory cells) are generally each configured in the form of a flip-flop circuit which is coupled to the lines of a bit line pair such as to be triggered into one of two possible directions in response to a small voltage change occurring on a bit line, to thereby amplify the voltage change. Such a flip-flop can be considered to consist of a pair of FETs having the gate electrodes respectively coupled to the lines of a bit line pair, the source electrodes respectively coupled to different lines of the bit line pair from the gate electrodes, and the source electrodes connected together at a common source node. Normally, the common source node is held at a voltage which will prevent triggering of the flip-flops, but when data read-out is to begin, the common source node is changed to a level which will permit triggering of the flip-flops in response to bit line voltage changes. However depending upon the polarity of a voltage change occurring on a bit line as a result of data read-out from a memory cell, the effective gate-to-source voltage that is applied to a transistor of a sense amplifier coupled to that bit line will differ. This can result in differing amounts of delay before amplification begins, since the common source node voltage is not immediately set to the level at which operation of the sense amplifiers can begin, but in practice will fall rather gradually with time, due to the effects of stray capacitance and supply lead resistance.
This bit line delay time problem is therefore a serious obstacle with regard to increasing the scale and element density of a DRAM semiconductor memory, and is a problem which has been difficult to overcome in the prior art.